Free Bedford Design Seminar May 16 Includes Remarks By MIT's Dr. Anatha P. Chandrakasan
Talk Addresses Issue of "Power Aware Systems"
SANTA CLARA, Calif. - May 14, 2002 - Sequence Design's free seminar this week in Bedford, Mass., on the challenges of low power/low voltage IC design and how to overcome them, features a keynote presentation from MIT's Dr. Anatha P. Chandrakasan, a faculty member since 1994 in the Department of Electrical Engineering and Computer Science.
Designers and engineering management from systems and semiconductor companies interested in registering for the May 16 seminar may do so online at:
http://www.sequencedesign.com/2_solutions/wp_forms/nanocoolseminar.html
In addition to Dr. Chandrakasan's remarks, seminar highlights include a luncheon, an overview of the NanoCool initiative from Sequence, and a presentation detailing NanoCool contributions from Circuit Semantics.
The NanoCool initiative, launched in March 2002, is a joint venture between semiconductor designers, EDA tool vendors, IP companies, and library suppliers, to provide a complete flow offering concurrent power management, timing and signal integrity capabilities to achieve rapid design closure at 130nm and below. In addition to Circuit Semantics, Virtual Silicon and Silicon Metrics are members of the initiative.
The issues being addressed in these seminars are growing in importance, as noted in the Feb. 27, 2002 issue of EE Times: "Power has indeed become the biggest challenge in IC design," said Gary Smith, chief EDA analyst at Gartner Dataquest.
"Sequence has a unique strategy . . . what they are doing is surrounding the IC implementation tool set, the idea being that in order to get rapid design closure, these tools leave a lot of performance on the table. By using the Sequence tools, you can eliminate a great deal of the slack."
For information on additional seminar locations, interested parties may contact a Sequence sales representative, or visit the Sequence website: http://www.sequencedesign.com/3_news/3b_events_nc.html
About Dr. Chandrakasan
Anantha P. Chandrakasan received the B.S, M.S. and Ph.D. degrees in Electrical Engineering and Computer Sciences from the University of California, Berkeley, in 1989, 1990, and 1994 respectively. Since September 1994, he has been at the Massachusetts Institute of Technology, Cambridge, and is currently an Associate Professor of Electrical Engineering and Computer Science. He held the Analog Devices Career Development Chair from 1994 to 1997. He received the NSF Career Development award in 1995, the IBM Faculty Development award in 1995 and the National Semiconductor Faculty Development award in 1996 and 1997. He has received several best paper awards including the 1993 IEEE Communications Society's Best Tutorial Paper Award, the IEEE Electron Devices Society's 1997 Paul Rappaport Award for the Best Paper in an EDS publication during 1997 and the 1999 Design Automation Conference Design Contest Award.
His research interests include the ultra low power implementation of custom and programmable digital signal processors, distributed wireless sensors, multimedia devices, emerging technologies, and CAD tools for VLSI. He is a co-author of the book titled "Low Power Digital CMOS Design" by Kluwer Academic Publishers and a co-editor of "Low Power CMOS Design" and "Design of High-Performance Microprocessor Circuits" from IEEE press.
He has served on the technical program committee of various conferences including ISSCC, VLSI Circuits Symposium, DAC, and ISLPED. He has served as a technical program co-chair for the 1997 International Symposium on Low-power Electronics and Design (ISLPED), VLSI Design '98, and the 1998 IEEE Workshop on Signal Processing Systems, and as a general co-chair of the 1998 ISLPED. He was an associate editor for the IEEE Journal of Solid-State Circuits from 1998 to 2001. He served as an elected member of the Design and Implementation of Signal Processing Systems (DISPS) Technical Committee of the Signal Processing Society. He was the Signal Processing Sub-committee chair for ISSCC 1999 through 2001. He is program vice-chair for ISSCC 2002.
Sponsors
Circuit Semantics, Inc. provides timing and characterization solutions for high performance cells, cores, and blocks based on innovative technology for which patents are currently pending. For more information: www.circuitsemantics.com.
Sun Microsystems, Inc. (Nasdaq: SUNW) is a leading provider of industrial-strength hardware, software and services that make the Net work. For more information: http://sun.com
Sequence Design, Inc., the SoC Design Closure CompanySM, develops RTL and physical design EDA tools to give its customers the competitive advantage to accelerate the turn-around time for their sub-180nm designs. For more information: sequencedesign.com.
For more information contact:
Jim Lochmiller
lochpr
(541) 552-0616
lochpr@yahoo.com
Greg Fawcett
Sequence Design Inc.
(408) 961-2365
gfawcett@sequencedesign.com
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